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CSE10033 Credits • All Sample & Full Unit Notes Unlocked
Computer Organization and Architecture
Von Neumann vs Harvard, 8 Great Ideas, Booth multiplication, instruction pipelining, cache memory hierarchy, and DMA.
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Unit 1
✓ LaTeX Notes & Formulas ReadyModule I: Introduction to Computer Architecture & Data Representation
Von Neumann vs Harvard, 8 Great Ideas, performance metrics, number systems, and Booth's multiplication algorithm.
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01
Von Neumann vs Harvard Architecture
Stored-program concept, memory bottle-neck, and architectural comparison. • ~20 mins
Sample Note (LaTeX)
1. Von Neumann vs Harvard Architecture (COA Assignment 1, Q2)
| Parameter | Von Neumann Architecture | Harvard Architecture |
|---|---|---|
| Bus Architecture | Single shared bus for instructions and data | Separate physical buses for instruction memory and data memory |
| Simultaneous Access | Cannot fetch instruction & operand at the same time | Fetches next instruction while executing data read/write |
| Memory Structure | Unified address space for code and data | Distinct address spaces for programs and data |
| Bottleneck | Von Neumann Bottleneck limits processor throughput | Eliminated data/instruction bus contention |
| Implementation Cost | Simpler control circuitry, lower pin count | Higher pin count and more complex circuit routing |
| Usage | General-purpose computing (x86, modern PCs) | DSPs, embedded microcontrollers (AVR, PIC, ARM Cortex-M) |
2. Eight Great Ideas in Computer Architecture (COA Assignment 1, Q3)
- Design for Moore's Law: Anticipate where silicon technology will be when chip development finishes.
- Use Abstraction to Simplify Design: Design in modular hierarchical layers to hide lower-level silicon complexities.
- Make the Common Case Fast: Optimize frequently executed instructions (e.g. integer adds, branch handling).
- Performance via Parallelism: Execute multiple operations concurrently using superscalar ALUs and multicore units.
- Performance via Pipelining: Overlap instruction execution stages (Fetch, Decode, Execute, Memory, Write-back).
- Performance via Prediction: Speculatively guess branch outcomes and start work earlier rather than stalling.
- Hierarchy of Memories: Exploit temporal and spatial locality with fast, small caches backed by larger, slower RAM.
- Dependability via Redundancy: Include spare modules (ECC parity, RAID) to recover transparently from hardware failures.
02
Eight Great Ideas in Computer Architecture
Moore's Law, abstraction, common case fast, parallelism, pipelining, prediction, memory hierarchy, redundancy. • ~20 mins
Non-Sample Note (LaTeX)
Eight Great Ideas in Computer Architecture (COA Assignment 1, Q3)
- Design for Moore's Law: Anticipate future transistor counts during long design cycles.
- Use Abstraction to Simplify Design: Modular hardware hierarchy hiding lower circuit gates.
- Make the Common Case Fast: Optimize instructions executed >80% of time (Amdahl's Law).
- Performance via Parallelism: Execute simultaneous operations via SIMD/multicore.
- Performance via Pipelining: Overlap instruction stages (Fetch, Decode, Execute).
- Performance via Prediction: Speculative branch execution rather than waiting for stall.
- Hierarchy of Memories: Fast small L1/L2 caches backing larger slower DRAM.
- Dependability via Redundancy: ECC memory and RAID disks to prevent catastrophic system crash.
03
Booth's Multiplication Algorithm
Signed 2's complement multiplication algorithm with arithmetic right shifts. • ~25 mins
Non-Sample Note (LaTeX)
1. Booth's Multiplication Algorithm
Multiplies signed binary integers in 2's complement representation.
- Let multiplicand be M, multiplier be Q.
- Extra 1-bit register Q-1 = 0, Accumulator A = 0.
- Step count n = ext{number of bits in } Q.
2. Booth's Decision Table
| Q0 | Q-1 | Action |
|---|---|---|
| 0 | 0 | Arithmetic Right Shift (A, Q, Q-1) |
| 0 | 1 | A = A + M, then Arithmetic Right Shift |
| 1 | 0 | A = A - M, then Arithmetic Right Shift |
| 1 | 1 | Arithmetic Right Shift (A, Q, Q-1) |
Arithmetic Right Shift (ASR) preserves the most significant sign bit of A.
3. Worked Example: Multiply (+7) imes (-3)
- M = +7 = 001112, -M = 110012, Q = -3 = 111012, n = 5 bits:
| Step | Operation | A | Q | Q-1 | Count |
|---|---|---|---|---|---|
| Initial | Load inputs | 00000 | 11101 | 0 | 5 |
| 1 | Q0 Q-1 = 10 implies A = A - M, ASR | 11100 | 11110 | 1 | 4 |
| 2 | Q0 Q-1 = 01 implies A = A + M, ASR | 00000 | 11111 | 0 | 3 |
| 3 | Q0 Q-1 = 10 implies A = A - M, ASR | 11100 | 11111 | 1 | 2 |
| 4 | Q0 Q-1 = 11 implies ext{ASR} | 11110 | 01111 | 1 | 1 |
| 5 | Q0 Q-1 = 11 implies ext{ASR} | 11111 | 00111 | 1 | 0 |
Result in A Q = 11111010112 = -2110 (Verified Correct!).
04
Floating-Point Representation (IEEE 754)
Sign bit, 8-bit biased exponent (bias 127), and 23-bit mantissa normalization. • ~25 mins
Non-Sample Note (LaTeX)
1. Single-Precision Format (32-bit Standard)
V = (-1)S imes (1.M) imes 2E - 127
- Sign Bit (S): 1 bit (0 = ext{positive}, 1 = ext{negative}).
- Biased Exponent (E): 8 bits, Bias = 28-1 - 1 = 127.
- Fraction / Mantissa (M): 23 bits (implicit normalized leading 1).
2. Conversion Example: Convert -118.62510 to IEEE-754 Single Precision
- Sign: Negative implies S = 1.
- Magnitude: 11810 = 11101102, 0.62510 = 0.1012 implies 1110110.1012.
- Normalize: 1.1101101012 imes 26.
- Biased Exponent: E = 6 + 127 = 133 = 100001012.
- Mantissa: 110110101000000000000002.
- Final 32-bit pattern:
1 10000101 11011010100000000000000=0xC2ECB400.